Multiples of integrated circuits are typically formed in a grid-like pattern on an active or front side of semiconductor substrate, such as silicon wafer. A metal layer is often deposited on a rear side of the wafer, opposite the front side. After formation of the integrated circuits, such as by photolithographic processes, for example, the wafer is separated or partitioned into a plurality of semiconductor chips by cutting or sawing the wafer along lines between the individual integrated circuits. This process often referred to as “dicing” or “singulating”.
As mentioned above, dicing is commonly performed by using a dicing blade to saw or grind the wafer between the individual integrated circuits of the grid, including the metal layer if present. However, sawing through the wafer in this fashion can create defects, such as cracking and chipping of the semiconductor material along the cut edges proximate to the rear side of the wafer, and chipping, cracking, and burring along the cut edges of the metal layer.
Such defects can adversely impact the electrical characteristics of the semiconductor chip and also diminish its physical stability which can create problems during subsequent die bonding processes. Tiny chips of semiconductor material and metal created by sawing can also disturb chip packaging processes. Additionally, cracks in the semiconductor chip, particularly in the semiconductor material, can interrupt contact between the semiconductor material and the metal layer, with such cracks also being known to propagate when the semiconductor chip is thermally cycled.
For these and other reasons, there is a need for an improved semiconductor wafer dicing or singulating process.